Access SPI Flash via memory map

[nimish]

Section 2.6 Memory Mapping in https://www.sony-semicon.co.jp/products/common/pdf/CXD5602_user_manual.pdf shows that there's a region of memory with "Data on SPI-Flash"

How/where is the 8MB of SPI Flash mapped into this 256MB region? Is it accessible?

[CamilaSouza]

Hey, @nimish
I actually don't know this one. I'm investigating internally and will get back to you once I have an answer.

[CamilaSouza]

Hey, @nimish
Unfortunately, because of security issue, we don’t open the memory mapped access by application CPUs.
Application CPU must request read from/write to the flash to M0P.

[nimish]

@CamilaSouza It would be better if the M0+ cpu enabled a window into the 4MB SPI flash or allowed r/w access without buffering in ram. The farapi to r/w files off the spi flash is not enough (fw_fm_rawread presumably).

It also cripples the processor when it comes to loading ML models or executables from storage. It's hard to see why the platform is advertised with 8MB flash if only half actually works and is not actually enabled for access per the manual.

Has SONY disabled any other core functionality?

[maxieaussie 0]

@CamilaSouza I have just opened a new topic about physically upgrading the QSPI flash memory chip with a bigger one (pin compatible and partially instruction compatible) . Any reason that you could think that it would not work? This would make the flash 256M instead of 8M
cheers

[CamilaSouza]

Hi, @maxieaussie-0
I already replied in the other post, but I'll just replicate the answer here for reference.

Physically upgrading the Flash will not work because Secure CPU defined fixed size of partitions, for SPK area and User area.
So even if you re-worked SPI Flash, it is the same size on software side.